Design and development of the Alice CRU user logic firmware for the mid readout chain

Abstract

A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider (LHC) at CERN is going through a major upgrade during which some of its subdetectors are replaced with new ones, while others are equipped with new electronics to handle the expected higher collision rates in the current running period (Run 3), which will start in 2022. As part of the upgrade, certain subdetectors such as the Muon Trigger (MTR), renamed to Muon Identifier (MID), now operate in a continuous, triggerless readout mode, in addition to the previous triggered readout mode. Due to the increased quantity of data, typical methodologies are impossible to employ without massive efforts to expand the processing capacity. Since the new ALICE computing system cannot keep up with the increased data flow of the MID, a new processing algorithm has to be established. The MID employs a Common Readout Unit (CRU) to interact with all subsystems of its new readout chain. The CRU, based on the PCIe40 hardware and the ARRIA 10 FPGA, is designed to meet the ALICE requirements. Its common firmware framework enables data taking in both continuous and triggered modes from most ALICE subdetectors and can be customized to meet the needs of any subdetectors through the use of a user logic component placed at the heart of the CRU firmware. This research project provides a new approach to processing the MID readout data based on the user logic component. Innovative methods for reducing the high bandwidth data rate and adaptations to ease data handling in the computing system have been introduced. In order to test and evaluate the user logic, a laboratory test bench equipped with a small-scaled MID readout chain has been developed at NRF iThemba LABS. Finally, the research findings and deliverables of this research can be used as a preliminary solution for a full-scaled user logic component, as well as by other postgraduate students for their studies.